Area and time efficient implementations of matrix multiplication on FPGAs

We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in [7] and [1] in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the designs in [7], [1], and our design are 14.45, 4.93, and 2.35, respectively, for 4 × 4 matrix multiplication. The latency of the design in [7] is 0.57μs, while our design takes 0.15μs using 18% less area. The area of our designs is smaller by 11%−46% compared with the best known systolic designs based on [9] with the same latency for the matrices of sizes 3×3−12×12. The performance improvements tend to grow with the problem size.